Sponsor
Portland State University provided funding, resources, space and support for this project. Some support by Ronald E. McNair Post baccalaureate Achievement Program of Portland State University, and the Korean Advanced Institute of Science and Technology, was given during parts of this project.
Document Type
Pre-Print
Publication Date
9-2005
Subjects
Reversible computing, Complementary metal oxide semiconductors, Computer software -- Verification, Formal methods (Computer science)
Abstract
We address the problem of test set generation and test set reduction, to first detect, and later localize faults occurring in reversible circuits. Reversible Computation has high promise of low power consumption. Some new fault models are first presented here. An explanation of the new fault models is made based on a physical realization representing the state of the art in the reversible CMOS circuit technology. Evidence is then presented showing that the fault models presented in the current literature are not adequate for existing realizations of reversible logic such as CMOS. We designed a ATPG software package with a friendly graphical user interface to aid experimentation with various fault models. The purpose of this work is to give an overview of our findings and pave the way for a later paper fully addressing the CMOS fault models. The key experimental results are presented.
Persistent Identifier
http://archives.pdx.edu/ds/psu/12771
Citation Details
Allen, Jeff S., Jacob D. Biamonte, and Marek A. Perkowski. "ATPG for reversible circuits using technology-related fault models." Proc 7th international symposium on representations and methodology of future computing technologies, RM2005, Tokyo, Japan. 2005.
Description
Originally presented at the 7th International Symposium on Representations and Methodology of Future Computing Technologies (RM2005), Tokyo, Japan, 5-6 September, 2005, and subsequently included in its proceedings.