Published In

VLSI Design

Document Type

Article

Publication Date

1999

Subjects

Logic synthesis, Logic circuits -- Design and construction

Abstract

New algorithms for generating a regular two-dimensional layout representation for multi-output, incompletely specified Boolean functions, called, Pseudo-Symmetric Binary Decision Diagrams (PSBDDs), are presented. The regular structure of the function representation allows accurate prediction of post-layout areas and delays before the layout is physically generated. It simplifies power estimation on the gate level and allows for more accurate power optimization. The theoretical background of the new diagrams, which are based on ideas from contact networks, and the form of decision diagrams for symmetric functions is discussed. PSBDDs are especially well suited for deep sub-micron technologies where the delay of interconnections limits the device performance. Our experimental results are very good and show that symmetrization of reallife benchmark functions can be done efficiently.

Description

This is the publisher's final PDF. Version of record can be found at http://www.hindawi.com/journals/vlsi/1999/085272/abs/ Copyright (1999) Hindawi

DOI

10.1155/1999/85272

Persistent Identifier

http://archives.pdx.edu/ds/psu/12902

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