Institution of Engineering and Technology
Delay lines, Logic circuits, Logic design
A new definition of semi-modularity to accommodate relative timing constraints in self-timed circuits is presented. While previous definitions ignore such constraints, the new definition takes them into account. The difference on a design solution for a well-known speed-independent circuit implementation of the Muller C element and a set of relative timing constraints that renders the implementation hazard free is illustrated. The old definition produces a false semi-modularity conflict that cannot exist due to the set of imposed constraints. The new definition correctly accepts the solution.
Park, Hoon; He, Anping; Roncken, Marly; and Song, Xiaoyu, "Semi-modular Delay Model Revisited in Context of Relative Timing" (2015). Electrical and Computer Engineering Faculty Publications and Presentations. 307.