Sponsor
Institution of Engineering and Technology
Document Type
Post-Print
Publication Date
2-2015
Subjects
Delay lines, Logic circuits, Logic design
Abstract
A new definition of semi-modularity to accommodate relative timing constraints in self-timed circuits is presented. While previous definitions ignore such constraints, the new definition takes them into account. The difference on a design solution for a well-known speed-independent circuit implementation of the Muller C element and a set of relative timing constraints that renders the implementation hazard free is illustrated. The old definition produces a false semi-modularity conflict that cannot exist due to the set of imposed constraints. The new definition correctly accepts the solution.
DOI
10.1049/el.2014.3666
Persistent Identifier
http://archives.pdx.edu/ds/psu/16853
Citation Details
Park, Hoon; He, Anping; Roncken, Marly; and Song, Xiaoyu, "Semi-modular Delay Model Revisited in Context of Relative Timing" (2015). Electrical and Computer Engineering Faculty Publications and Presentations. 307.
http://archives.pdx.edu/ds/psu/16853
Included in
Computer Engineering Commons, Computer Sciences Commons, Electrical and Computer Engineering Commons
Description
This is the author’s version of a work that was accepted for publication in Electronics Letters. Changes resulting from the publishing process, such as peer review, editing, corrections, structural formatting, and other quality control mechanisms may not be reflected in this document.
A definitive version was subsequently published in Electronics Letters, vol. 51, no. 4, pp. 332-334 and can be found online at: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7042452&isnumber=7042371