Memristor Panic—A Survey of Different Device Models in Crossbar Architectures
This work was supported by the National Science Foundation under award # 1028378 and by the Defense Advanced Research Projects Agency (DARPA) under award # HR0011- 13-2-0015.
2015 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)
Memristors, Semiconductors -- Mathematical models, Algorithms, Biologically-inspired computing
The popularity of memristors has led to a wide range of models being proposed for both physically realized devices and their concepts in general. These models have been fit to specific devices, but the resulting device models are not often discussed in relation to specific applications. A common tool in neuromorphic algorithms, crossbar architectures rely exclusively on the electrical properties of the device connecting rows to columns. Using memristors for these connections, we investigate the viability of 14 device models found in literature for this application. We look at these device models in a crossbar architecture, with supporting circuitry clocked at 500 MHz and providing voltages up to 4V. The two primary functions of a crossbar, evaluating and updating, are both addressed in the context of Rozell et al.'s neuromorphic, Locally Competitive Algorithm (LCA) learning the MNIST dataset and are used to identify the practical qualities of different memristor models. We establish guidelines for designing crossbars regardless of individual device characteristics, and identify a class of devices that produce energy savings when write voltage is relaxed. Our analysis is aimed at assisting researchers with the selection of an appropriate device model, and informing device manufacturers of critical qualities needed from memristive devices for these applications.
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Researchers can access the work here: http://dx.doi.org/10.1109/NANOARCH.2015.7180595
Woods, Walt, Mohammad Mahmoud A. Taha, S. J. Dat Tran, Jens Burger, and Christof Teuscher. "Memristor panic—A survey of different device models in crossbar architectures." In Nanoscale Architectures (NANOARCH), 2015 IEEE/ACM International Symposium on, pp. 106-111. IEEE, 2015.