Pareto Optimal Mapping for Tile-based Network-on-Chip under Reliability Constraints
Published In
International Journal of Computer Mathematics
Document Type
Citation
Publication Date
2015
Subjects
Mathematical optimization, Algorithms, Networks on a chip, Swarm intelligence
Abstract
Mapping for network-on-chip (NoC) is one of the key steps of NoC design. To improve the performance and reliability of NoC architectures, we present a comprehensive optimization algorithm with multiple objectives. We propose to find the Pareto optimal solutions, rather than a single solution usually obtained through scalarization, e.g. weighting the objective functions. In order to meet the NoC mapping requests and strengthen the capability of searching solutions, the standard particle swarm optimization (PSO) algorithm is improved and a fault-tolerant routing is proposed. These methods help to solve the tradeoff between high performance and system reliability. We present a mathematical analysis of the convergence of the improved algorithms, and prove sufficient conditions of convergence. The improved algorithms are implemented on the Embedded Systems Synthesis Benchmarks Suite (E3S). Experimental results show our algorithms achieve high performance and reliability compared with the standard PSO.
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Unaffiliated researchers can access the work here: http://dx.doi.org/10.1080/00207160.2014.892073
DOI
10.1080/00207160.2014.892073
Persistent Identifier
http://archives.pdx.edu/ds/psu/20915
Citation Details
Le, Q., Yang, G., Hung, W. N., Song, X., & Zhang, X. (2015). Pareto optimal mapping for tile-based network-on-chip under reliability constraints. International Journal of Computer Mathematics, 92(1), 41-58.
Description
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