First Advisor

Dan Hammerstrom

Date of Publication

Winter 3-26-2013

Document Type

Thesis

Degree Name

Master of Science (M.S.) in Electrical and Computer Engineering

Department

Electrical and Computer Engineering

Language

English

Subjects

Neural computers -- Design and construction, Cognitive science -- Research, Artificial intelligence -- Computer simulation

DOI

10.15760/etd.639

Physical Description

1 online resource (xi, 91 pages)

Abstract

This thesis presents a design to route the spikes in a cognitive computing project called Systems of Neuromorphic Adaptive Plastic Scalable Electronics (SyNAPSE). SyNAPSE is a DARPA-funded program to develop electronic neuromorphic ma- chine technology that scales to biological levels. The basic computational block in the SyNAPSE system is the asynchronous spike processor (ASP) chip. This analog core contains the neurons and synapses in a neural fabric and performs the neural and synaptic computations.An ASP takes asynchronous pulses (spikes) as inputs and after some small delay produces asyn- chronous pulses as outputs.The ASP chips are organized in a nxn (where n [approximately equal to] 10) 2-dimensional grid with a dedicated node for each chip. This interconnected network is called Digital Fabric(DF) and the node is called Digital Fabric Node (DFN). The DF is a packet network that routes pulse (AER - Address event rep- resentation) packets between ASP's. This thesis also presents a technique for design implementation on a FPGA, perfor- mance testing of the network and validation of the network using various tools.

Rights

In Copyright. URI: http://rightsstatements.org/vocab/InC/1.0/ This Item is protected by copyright and/or related rights. You are free to use this Item in any way that is permitted by the copyright and related rights legislation that applies to your use. For other uses you need to obtain permission from the rights-holder(s).

Persistent Identifier

http://archives.pdx.edu/ds/psu/9281

Download

Share

COinS