Published In

Proc. 4th International Workshop on Applications of the Reed-Müller Expansion in Circuit Design (Reed-Müller 99), University of Victoria, Victoria B.C., Canada, August 20-21, 1999.

Document Type

Conference Proceeding

Publication Date

1999

Subjects

Reversable Logic, Reversable computing, Logic Synthesis

Abstract

We present new experimental Windows 95/98/NT software for investigation of graph properties of boolean (in particular, Reed-Muller) logic with an equal number n of inputs and outputs (called movement functions). Realized at the input of an n-bit register, such functions create autonomous Finite State Machines (FSMs). TRACE software system allows the user to visualize State Transition Graphs (STGs) of the autonomous FSMs. Other features of TRACE help explore graph properties of function families. These families are produced by a generic function, differing from it only in the order of components, one operation, or one literal (this literal is complemented or replaced by another literal). The autonomous FSMs are used to implement economically next-state logic of realtime control units such as CPU controllers. A case study using TRACE to build economical, highly testable reversible counters based on linear Reed-Muller polynomials is given.

Description

Paper originally presented at the: 4th International Workshop on Applications of the Reed-Müller Expansion in Circuit Design,University of Victoria, Victoria B.C., Canada, August 20-21, 1999. Subsequently published as: Proc. International Workshop on Applications of the Reed-Müller Expansion in Circuit Design (Reed-Müller 99), University of Victoria, Victoria B.C., Canada, August 20-21 1999.

Persistent Identifier

http://archives.pdx.edu/ds/psu/12983

Download

Share

COinS