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Proceedings ICCIMA'98 Conference

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Logic synthesis, Logic circuits -- Design and construction


Regular layout is a fundamental concept in VLSI design which can have application in custom design for submicron technologies, designing new architectures for fine-grain Field Programmable Gate Arrays (FPGAs) and Electrically Programmable logic Devices (EPLDs), and minimization of logic functions for existing FPGAs. PLAs are well known examples of regular layouts. Lattice diagrams are another type of regular layouts that have been recently introduced for layout-driven logic synthesis. In this paper we extend and combine theses two ideas, by introducing the multi-level PLA-like structures, composed from multi-output (pseudo) symmetrical lattice planes and other planes (multi-input, multi-output regular blocks). The main idea is to decompose a non-symmetric general function to planes, in order to realize as much as possible of the function with totally symmetric and regularly connected planes.


Preprint of an article submitted for Proceedings ICCIMA'98 Conference (pp. 707-720). Copyright (1998) World Scientific Publishing Company

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