Tutorial 2A: 3D Integration - Challenges and Advantages
2016 29th IEEE International System-on-Chip Conference (SOCC)
The most significant challenge for continued integration of complex systems is energy efficiency. 3D heterogeneous stacking of diverse circuit blocks is one of the most promising solutions. The tutorial will focus on three-dimensional integrated circuits (3D ICs) consisting of multiple layers of systems integrated vertically using through silicon vias (TSVs). We will discuss advantages and challenges of current 3D TSV-based technologies and how to exploit various options through tradeoffs and well-educated choices for designing energy efficient heterogeneous systems. Comparisons between various TSV models and layout solutions will be presented and discussed. Influence of TSV-induced thermo-mechanical stress on devices and interconnects will be discussed. Influence and design trade-offs of temperature distribution on system performance and power dissipation will be discussed. As time permits we will also look towards the horizon, exploring monolithic 3D systems, a variety of new materials such as carbon-nanotubes, and the potential of an abundance of energy efficient interconnects.
Locate the Document
M. Chrzanowska-Jeske and J. Becker, "Tutorial 2A: 3D integration - challenges and advantages," 2016 29th IEEE International System-on-Chip Conference (SOCC), Seattle, WA, 2016, pp. 1-3.