Title

Evaluation of the Operation of Depletion-Mode SiC Power JFET in DC-DC Converter Applications

Published In

International Convention on Information and Communication Technology, Electronics and Microelectronics

Document Type

Presentation

Publication Date

May 2014

Abstract

This paper presents the system for the evaluation of operation of a depletion-mode silicon carbide (SiC) power junction field-effect transistor (JFET). The main part of the system is a dc-dc step-down converter which represents realistic operating conditions for the switching devices in a synchronous buck configuration. In order to test the importance of the dead-time value on the operation and efficiency of the synchronous buck converter, a precise two-channel time-delay pulse signal generator is developed and its operation is described. The ability to precisely regulate control signal parameters of the high-side FET and low-side FET (switching voltage and current, operating frequency, duty cycle, dead-times, etc.) is needed in order to fully characterise SiC power switches. The functionality of the complete system is verified by measurements performed under various operating conditions.

DOI

10.1109/MIPRO.2014.6859547

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