Buffered-Interconnect Performance and Power Dissipation in 3D ICs with Temperature Profile

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2018 IEEE International Symposium on Circuits and Systems (ISCAS)

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We generate, then analyse and evaluate the buffered interconnect performance and power dissipation in 3DICs with vertical temperature distribution. Wire distribution in all device layers in 3D ICs is generated at the floorplanning level. The floorplanner optimizes simultaneously blocks' and TSV islands' locations to reduce delay and power. We assume a heat sink is located at the bottom of the stack and temperature increases up the stacked layers. We noticed that weak increase in wire delay with temperature reduces the buffer insertion length and rises the number of needed buffers. More buffers with a considerable increase in buffer delay and leakage power impacts interconnect performance. It is shown that without including vertical temperature profile a prediction of 3D ICs performance and power dissipation could be strongly over- or underestimated. It also means that quality of 3D layout solutions generated during early optimization stages of physical design can be questionable. The percentage of overestimation and underestimation depend on location of the heatsink, the temperature profile and the benchmark itself. In tested benchmarks, we noticed up to 55% underestimation of the interconnect delay, 31% in buffer count and 63% and higher in interconnect power consumption as compared to typically used room-temperature interconnect parameters' values.


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