Non-Temporal Logic Performance of an Atomic Switch Network

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2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)

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Efforts to achieve a low-power, dynamically complex system become crucial as CMOS fabrication limits are realized. Atomic Switch Networks (ASNs) provide fabrication advantages over traditional CMOS through the combination of top-down and bottom-up techniques, leading to densely inter-connected networks of atomic switches. ASNs show emergent behaviors through the interaction of individual non-linear elements. These properties make ASNs suitable for alternative computational paradigms, such as neuromorphic or reservoir computing. This work examined ASNs' ability to perform Boolean logic operations using non-temporal inputs based on randomized Boolean input streams. Zero and one bits were converted to negative and positive DC voltage pulses, respectfully. Next, a linear readout layer was applied to an array of voltage outputs from the device to reconstruct target output signals for the given task. ASNs produced nearly perfect results at low voltages for AND, OR, and NAND with more than 95% confidence. XOR, which requires non-linearity to solve, was able to be partially solved at high voltages with more than 95% confidence. As opposed to previous works which have investigated temporal computation in ASNs, this work was the first to demonstrate semi-predictable, non-temporal, non-linear behavior within the device. Results demonstrated that the device connectivity is complete enough to perform complex computations.


©2017 IEEE



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