Fast Buffer Count Estimation in 3D IC Floorplanning
Published In
IEEE Transactions on Circuits and Systems II: Express Briefs
Document Type
Citation
Publication Date
8-6-2020
Abstract
A methodology for fast and accurate estimation of the number and positions of buffers during 3D IC floorplanning is developed. Our algorithm computes candidate buffer positions simultaneously with assignment of 3D nets to TSVs. Through accurate delay characterization of buffered 3D nets, the minimum distance between consecutive buffers is estimated. Additionally, an analytical approach is used to find the optimal position of buffers in front of TSVs. This prevents additional buffers’ insertion around TSVs, incurring lesser delay and power in 3D nets. Experimental results with expanded GSRC benchmarks show 5.6% more reduction in number of buffers, 5.7% reduction in interconnect delay and 4% reduction in dynamic power, compared to a previous published work. The potential impact of nanoscale TSVs on buffer estimation at sub-45 nm technologies is analyzed.
Locate the Document
DOI
10.1109/TCSII.2020.3007858
Persistent Identifier
https://archives.pdx.edu/ds/psu/34800
Publisher
IEEE
Citation Details
Mohapatra, S., Vendra, S. K., & Chrzanowska-Jeske, M. (2020). Fast Buffer Count Estimation in 3D IC Floorplanning. IEEE Transactions on Circuits and Systems II: Express Briefs, 1–1. https://doi.org/10.1109/tcsii.2020.3007858
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