Integrated circuits -- Computer simulation, Three-dimensional integrated circuits -- Design and construction
Physical size limitations in miniaturizing two-dimensional (2D) transistors are becoming more difficult to overcome. In order to continue increasing the processing power of electronic circuits, new design paradigms are needed. Three-dimensional (3D) architectures provide a solution to this issue and are currently being implemented via wafer stacking. However, more significant gains in terms of packing and speed can be achieved by CMOS components with truly integrated 3D cellular architectures. One of these is the Cell Matrix, a self-configurable defect- and fault-tolerant architecture, which is ideally suited for ultra large-scale integration. For this project, we worked to expand the Cell Matrix models and tools from 3D cubes to a 3D truncated octahedron geometry. The main goal of our explorative study is to quantify the trade-off between complexity and simplicity of various 3D geometries that would lead to economical and efficiency improvements in true 3D integrated circuits. An additional goal is to design virtual reality tools that would allow designing and visualizing 3D circuits more intuitively and naturally.
Udall, Jeffrey, "3D FPGA Cell Matrix by Self-assembly" (2016). Undergraduate Research & Mentoring Program. 2.