Microstructure Signature Evolution in Solder Joints, Solder Bumps, and Micro-Bumps Interconnection in A Large 2.5D FCBGA Package during Thermo-Mechanical Cycling

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2019 IEEE 69th Electronic Components and Technology Conference (ECTC)

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Large body-size and heterogeneously integrated packages have become essential for high-performance computing applications. As an example, designs such as silicon interposer-based 2.5D packages have enabled the integration of high-performance silicon and memory in close proximity, greatly increasing the bandwidth and throughput of these devices. Within such a package, the interaction among the many sub-components and materials creates a complex thermo-mechanical response in the interconnections, which includes micro-bumps and C4 bumps. In addition, such components frequently require a high-layer count and high-thickness PCB, which creates a challenge for the reliability of the solder joints. As a result, the overall reliability of PCB assembly needs to be evaluated at every level of the interconnect. In this study, a large 2.5D flip chip package was subject to temperature cycling testing. This component was also attached to a PCB, and the entire assembly went through temperature cycling as well. Over the duration of testing, a series of microstructure evaluations were performed at the micro-bump, C4 bump, and solder joint level. Each analysis included polarized optical imaging, SEM (Scanning Electron Microscope), EBSD (Electron Backscatter Diffraction) and strain contour analysis. With these techniques, the methodology was able to not only observe the degradation and microstructure evolution, but was also able to reveal the damage by collecting high-resolution strain / stress distribution data at critical locations such as corner bumps and solder joints. These data provided insight into metallurgical processes that alter the grain structure of solder joints at different dimensions and locations, and ultimately the details of the failure mechanisms and processes.


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