Stress and Strain Level Evolution and Correlation to Void Migration in Solder Bumps After Various Thermo-Mechanical Post Treatments

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2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)

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With large silicon die size and increased performance demands of computer, graphics, and server applications, the thermo-mechanical stability of the die-level solder bump interconnects are increasingly critical. Since all solder bump interconnects experience a melting and solidification during the package manufacturing and board assembly processes, an initially high residual stress at the interconnection is expected, changing during device operation and aging. Even though solder bumps typically show limited defects at time-zero, characterization of their initial states and the evolution of the stress and strain states are crucial for assessment of potential reliability risks. This study is focused on evolution of the stress and strain levels per solder bump, and their levels of change during various post-treatments including pre-conditioning, high temperature storage, and thermal cycling. For direct stress and strain measurements, electron-backscatter diffraction (EBSD) was used with local mis-orientation and strain contour mapping. EBSD analysis of selected rows of solder bumps at each reliability test condition revealed that initial microstructure plays a major role in the stress and strain development, deformation percentage, grain spread, and local mis-orientation per solder bump. Further, the correlation between the pre-existing micro-voids and the stress state per solder bumps suggests a driving force for possible micro-void migration within the solder bumps.



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