First Advisor

Y. C. Jenq

Date of Publication


Document Type


Degree Name

Doctor of Philosophy (Ph.D.) in Electrical and Computer Engineering


Electrical Engineering




Signal processing -- Digital techniques, SONET (Data transmission), Fuzzy sets, Computer algorithms



Physical Description

2, x, 124 leaves: ill. 28 cm.


Excessive high-frequency jitter or low-frequency wander can create problems within synchronous transmission systems and must be kept within limits to ensure reliable network operation. The emerging Synchronous Optical NETwork (SONET) introduces additional challenges for jitter and wander attenuation equipment (called desynchronizers) when used to carry payloads from the existing Plesiochronous Digital Hierarchy (PDH), such as the DS3. The difficulty is primarily due to the large phase transients resulting from the pointer-based justification technique employed by SONET (called Pointer Justification Events or PJEs). While some previous desynchronization techniques consider the buffer level in their control actions, none has explicitly considered wander generation. Instead, compliance with jitter, wander, and buffer-size constraints have typically been met implicitly--through testing and tuning of the Phase Locked Loop (PLL) controller. We investigated a fuzzy/rule-based solution to this desynchronization/constraint-satisfaction problem. But rather than mapping the input state to an action, as is done in standard fuzzy logic, our controller maps a state and a candidate action to a desired result. In other words, this control paradigm employs prediction to evaluate which of a set of candidate actions would result in the "best" predicted performance. Before the controller could predict an action's affect on buffer and wander levels, appropriate models were required. The model of the buffer is simply the integral of the frequency difference between the input and output of the PLL, and a novel MTIE Constraint Envelope technique was developed to evaluate future wander performance. We show that a predictive knowledge-based controller is capable of achieving the following three objectives: (1) Reduce jitter implicitly by avoiding unnecessary frequency changes such that the jitter limits specified in relevant standards are met, (2) Explicitly satisfy both buffer-level and wander (MTIE) constraints by trading off performance in one to meet the hard limit of the other, (3) When both buffer-level and wander constraints are in danger of violation and cannot be satisfied simultaneously, maintain the preferred constraint by sacrificing the other. We also show that the computation required for this control algorithm is easily within the reach of modern microprocessors.


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