Advisor

Xiaoyu Song

Date of Award

Winter 2-13-2013

Document Type

Thesis

Degree Name

Master of Science (M.S.) in Electrical and Computer Engineering

Department

Electrical and Computer Engineering

Physical Description

1 online resource (vii, 65 pages)

Subjects

Low voltage integrated circuits -- Energy consumption, Asynchronous circuits -- Design and construction, Logic circuits

DOI

10.15760/etd.211

Abstract

In modern integrated circuits, one way to reduce power consumption is to turn off power to parts of the circuit when those are idle. This method is called power gating. This thesis presents a state-preserving technique to achieve power savings in GasP family of asynchronous circuits by turning off the power when the circuit is idle. The power control logic turns on the power in anticipation of the receiving data. The power control logic turns off the power when the stage is idle either because it is empty or because the pipeline is clogged. The low logical effort of GasP circuits makes just-in-time power gating possible on a stage-by-stage basis. A new latch called Lazy Latch is introduced in this thesis. The lazy latch preserves its output and permits power gating of its larger transistors. The lazy latch is power efficient because it drives strongly only when necessary. A new latch called Blended Latch is proposed in this thesis which blends the advantages of the Conventional latches and the Lazy latches. Performance of power gating is evaluated by comparing the power-gated pipeline against the non-power gated pipeline. Power savings achieved are dependent on the duty cycle of operation. The fact that just-in-time power gating achieves power savings after it is idle for a minimum of 106 cycles makes it useful in limited applications where a quick start is required after long idle times.

Persistent Identifier

http://archives.pdx.edu/ds/psu/9306

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