First Advisor

W. Robert Daasch

Date of Publication


Document Type


Degree Name

Master of Science (M.S.) in Electrical and Computer Engineering


Electrical and Computer Engineering




Complementary Metal oxide semiconductors -- Testing, Complementary Metal oxide semiconductors -- Thermal properties, Application-specific integrated circuits -- Testing, Application-specific integrated circuits -- Thermal properties, Integrated circuits -- Design and construction



Physical Description

1 online resource (114 p.) : ill. (some col.)


Among the many efforts to improve the IC test process are tests that attempt to differentiate between healthy and defective or low reliability ICs by manipulating the operating conditions of the IC being tested. This thesis attempts to improve the common understanding of multiple and targeted temperature testing by evaluating work published on the subject to date and by presenting previously unpublished empirical observations. The empirical observations are made from SCAN and LBIST based MinVDD measurements, Static IDD measurements, as well as parametric measurements of transistor characteristics. The test vehicles used are 0.25μm and 0.18μm CMOS ASICs fabricated by LSI Logic. An IC’s performance is bound by a three dimensional space defined by VDD, frequency, and temperature. A model is presented to explain the boundaries of the performance region in terms of the ability of the IC’s constituent transistors to provide power and the Zero-Temperature-Coefficient (ZTC). Also, it is determined that multiple temperature testing can add new tests to current test suites to improve the resolution between healthy and defective ICs.


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Portland State University. Dept. of Electrical and Computer Engineering

Persistent Identifier