Sponsor
Portland State University. Department of Electrical and Computer Engineering
Advisor
W. Robert Daasch
Date of Award
1988
Document Type
Thesis
Degree Name
Master of Science (M.S.) in Electrical and Computer Engineering
Department
Electrical and Computer Engineering
Physical Description
1 online resource (91 p.)
Subjects
Electric resistance -- Mathematical models, Metal oxide semiconductors -- Mathematical models
DOI
10.15760/etd.5686
Abstract
The voltage controlled resistance model is developed for a reliable MOS transistor resistance mapping. The model includes both system and local parameters, and incorporates the effect of rise and fall time variations on the gate delay. MOS transistor resistance mapping is applied in logic simulation and timing verification. Also, it can be used in automatic transistor sizing and critical path analysis.
Persistent Identifier
http://archives.pdx.edu/ds/psu/21270
Recommended Citation
Jia, Joey Zong-yi, "Voltage controlled resistance model for MOS transistors" (1988). Dissertations and Theses. Paper 3802.
https://pdxscholar.library.pdx.edu/open_access_etds/3802
10.15760/etd.5686
Description
If you are the rightful copyright holder of this dissertation or thesis and wish to have it removed from the Open Access Collection, please submit a request to pdxscholar@pdx.edu and include clear identification of the work, preferably with URL