Portland State University. Department of Electrical Engineering
W. Robert Daasch
Date of Publication
Master of Science (M.S.) in Electrical and Computer Engineering
Electric resistance -- Mathematical models, Metal oxide semiconductors -- Mathematical models
1 online resource (91 p.)
The voltage controlled resistance model is developed for a reliable MOS transistor resistance mapping. The model includes both system and local parameters, and incorporates the effect of rise and fall time variations on the gate delay. MOS transistor resistance mapping is applied in logic simulation and timing verification. Also, it can be used in automatic transistor sizing and critical path analysis.
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Jia, Joey Zong-yi, "Voltage controlled resistance model for MOS transistors" (1988). Dissertations and Theses. Paper 3802.