First Advisor

Malgorzata Chrzanowska-Jeske

Term of Graduation

Summer 2020

Date of Publication

8-17-2020

Document Type

Dissertation

Degree Name

Doctor of Philosophy (Ph.D.) in Electrical and Computer Engineering

Department

Electrical and Computer Engineering

Language

English

Subjects

Three-dimensional integrated circuits -- Design and construction, Interconnects (Integrated circuit technology), Integrated circuits

DOI

10.15760/etd.7437

Physical Description

1 online resource (xvii, 150 pages)

Abstract

Through-silicon via (TSV)-based three-dimensional integrated circuits (3D ICs) are expected to be the breakthrough technology for keeping up with the scaling trends of Moore's law, while also offering the unique opportunity for functional diversification through heterogenous integration. TSVs are vertical metal interconnects enabling communication across stacked and thinned dies. The dramatic reduction in global wirelength and chip footprint in 3DICs, directly improves delay, device density, bandwidth and routing congestion. Even with the current maturation of TSV process, the roadmap for industry adoption of 3DICs remains largely uncertain due to lack of standardized 3D tools capable of handling the sheer complexity of the three-dimensional solution space.

Many critical design issues arise due to usage of TSVs. Large-sized TSVs, introduce significant area and delay overhead. The increased risk of TSV failure during fabrication or bonding, causes long-term reliability issues and loss of yield. The earlier these critical issues are addressed in the design cycle, the better our chances are of making realistic performance predictions and informed decisions, for speeding-up convergence. 3D floorplanning constitutes an important first step of layout design, providing early feedback on critical performance metrics, i.e., area, wirelength, delay, power and wiring density. Since the resulting floorplan impacts the optimization of all subsequent stages, there is a critical need for efficient TSV-aware layout design exploration tools, which can accurately characterize the physical and electrical impact of TSVs.

A key concept of this thesis is that interconnect performance in 3D chips is directly controlled by the quality of the generated 3D floorplan, which is fundamentally impacted by the heuristics guiding the search and evaluation of floorplan. In support of this view, the core objective of this thesis is to develop an efficient methodology to improve the 3D floorplan solution quality. By generating more realistic 3D layouts, we seek to improve the accuracy of evaluation of the goodness of a 3D floorplan. A new dynamic TSV clustering algorithm is introduced, which simultaneously optimizes the sizes and positions of TSV clusters on the layout. This is the first work to consider the direct minimization of TSV occupied area at the floorplanning stage. As the generated floorplan is independent of any fixed arrangement of TSVs as input, it facilitates a more realistic and accurate evaluation of floorplan metrics. A novel nets-to-TSVs assignment algorithm which considers the inherent trade-off between TSV area and the TSV capacitance during net delay optimization, is also included. Experimental results with GSRC benchmarks show average 25% reduction in TSV footprint for all benchmarks, as compared to the single TSV placement approach. Compared to floorplanning with fixed-sized TSV islands, the approach reduces total chip area by average 7.6% and total interconnect delay by average 9%.

In this thesis, early estimation of buffers is directly incorporated with assignment of nets to TSVs. The candidate location of buffers in individual 3D nets is estimated by simultaneously considering the TSVs' RC parasitics, positions of TSVs along the 3D net and size of the cluster containing the TSVs. This results in a more reliable estimate of buffers, interconnect delay and power. Secondly, an analytical approach for estimating the optimal position of buffers around TSVs is developed, which helps in avoiding excessive usage of buffers around TSVs.

The extent to which chip performance is influenced due to negative impact of TSVs, is also determined by the process technology used to fabricate 3D ICs. This important design concern is addressed, by including the impact of future nano-CMOS technologies on early estimation of area, number of buffers, total delay and power. Further insight is gained on the impact of nano-scale TSVs on design quality, when combined with different nanometer technologies.

A new TSV redundancy scheme is incorporated in the floorplanner, for increasing the fault-tolerance of TSV clusters and improving the overall reliability of the design. Assuming a uniform TSV failure rate and an independent TSV defect distribution, a minimum required number of spare TSVs are allocated for the given size of TSV cluster, such that a cluster is fully repairable. Unlike previous works on TSV redundancy based on fixed layouts, the proposed scheme does not incur additional TSV area overhead due to allocation of spare TSVs.

Rights

In Copyright. URI: http://rightsstatements.org/vocab/InC/1.0/ This Item is protected by copyright and/or related rights. You are free to use this Item in any way that is permitted by the copyright and related rights legislation that applies to your use. For other uses you need to obtain permission from the rights-holder(s).

Persistent Identifier

https://archives.pdx.edu/ds/psu/33672

Available for download on Tuesday, August 17, 2021

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