First Advisor

John M. Acken

Term of Graduation

Winter 2021

Date of Publication


Document Type


Degree Name

Doctor of Philosophy (Ph.D.) in Electrical and Computer Engineering


Electrical and Computer Engineering




Memristors -- Testing



Physical Description

1 online resource (xii, 140 pages)


Moore's law decline has paved the way to shift to new technologies at architectural and device levels. CMOS based technologies are facing many challenges with the growing demand for miniaturization. The growing heat dissipation is the major limitation for performance, energy efficiency and reliability with the increasing transistor count in integrated circuits. Manufacturing costs and process/memory performance gap have also grown steadily over the last several decades with the scaling down of the CMOS feature size. Memristor, a nanoscale device, has the potential to address the CMOS limitations because of its non-volatility, high density, low power operation, low cost per bit and CMOS compatibility. The high density memristor crossbar structures are widely considered for performing memory operations, logic, stochastic and neuromorphic computations. However, these memristor based devices are prone to defects because of the non-deterministic nature of nano-scale fabrication. The motivation of my research is to develop an application independent methodology for testing memristor circuits for fault detection and fault diagnosis using a unique property of memristor crossbar circuits' sneak paths. Sneak paths are paths for current parallel to the intended path occurring in memristor crossbar architectures. This research characterizes sneak paths and sneak path currents as a function of size of the array, resistance values, input voltage and I/O switch vector. The equations I derived enable us to predict the sneak paths and sneak path currents for various array sizes to determine the constraints to resistive memristor circuits. The sneak path characterization work provides boundary conditions for applications that use memristor crossbar arrays and provides insights into memristor crossbar testing. Using this characterization, a fault detection method is presented in the dissertation for fault detection of stuck-at low resistance and stuck-at high resistance faults using long sneak paths to result in shorter test vector sets. Long length sneak paths that enable fault detection with shorter test vector sets leads to improved test time. As the crossbar array size increases, the length of the longest possible sneak paths would also increase leading to improved test time compared to March testing. My fault diagnosis method using fault dictionary approach with improved test time is another highlight of this research. The results were demonstrated using LTspice simulations on resistive memristor crossbar circuits by varying resistance programming, IO switch-vectors, input voltage and size of the array. The fault detection approach used for stuck-at LRS and stuck-at HRS fault detection is extended to test intermediate faults in memristor crossbar circuits. The method of selecting the detection limit for testing intermediate faults in crossbar circuits is presented in the dissertation using crossbar array simulations.


© 2021 Rasika Dhananjay Joshi

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