First Advisor

Sung Yi

Date of Publication

Spring 6-13-2014

Document Type

Thesis

Degree Name

Master of Science (M.S.) in Mechanical Engineering

Department

Mechanical and Materials Engineering

Language

English

Subjects

Chip scale packaging, Electronic apparatus and appliances -- Thermal properties, Electronic packaging, Electronics -- Materials -- Research

DOI

10.15760/etd.1781

Physical Description

1 online resource (viii, 70 pages)

Abstract

One of the main challenges in the electronics manufacturing and packaging development is how to integrate more functions inside the same or even smaller size. To meet the demand for higher integration, the interest toward passive and active component embedding has been increasing during the past few years. One of the main reasons for the growing interest toward embedded active components, in addition to demand for higher packaging density, is the need for better electrical performance of the component assemblies. However, it is little known how embedded IC and passives affect the reliability of IC packaging.

Solder joints have been used in the electronic industry as both structural and electrical interconnections between electronic packages and printed circuit boards (PCB). When solder joints are under thermal cyclic loading, mismatch in coefficients of thermal expansion (CTE) between the printed circuit boards and the solder balls creates thermal strains and stresses on the joints, which may finally result in cracking. Consequently, the mechanical interconnection is lost, leading to electrical failures (such as hard/intermittent open, parametric failure), which in turn causes malfunction of the circuit or whole system.

When a die is embedded into a substrate, Young's modulus of the die is larger than one of the core of the substrate and the CTEs of the die is smaller than those of the substrate. As a result, mismatch in coefficients of thermal expansions (CTE) between the substrate with the embedded device and the solder balls may increase.

In the present study, the stress of chip scale packages (CSP) with an embedded die under thermal cycling conditions is evaluated using the finite element method. The viscoplastic model for solders including matrix dislocation mechanism and grain boundary sliding model developed by Yi et al. (2002) is employed.

Rights

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Persistent Identifier

http://archives.pdx.edu/ds/psu/12030

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