SCBench: A Benchmark Design Suite for SystemC Verification and Validation

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SystemC has become a de-facto standard hardware modelling language in the semiconductor industry, enabling early exploration of design spaces and verification at a higher level of abstraction. It is both important and necessary for researchers to evaluate their new verification approaches and algorithms quantitatively. This paper presents SCBench, a comprehensive suite of benchmark designs for SystemC verification and validation. SCBench consists of 38 well-written representative behavior-level SystemC designs, which have been selected carefully from various application domains, such as CPU architecture, security, network, and artificial intelligence. The benchmark covers most core features of SystemC language. SCBench is freely available online to all researchers. Source: 2018 23RD ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 440-445 2018


NOTICE: this is the author’s version of a work that was accepted for publication in Design Automation Conference (ASP-DAC), 2018 23rd Asia and South Pacific. Changes resulting from the publishing process, such as peer review, editing, corrections, structural formatting, and other quality control mechanisms may not be reflected in this document. Changes may have been made to this work since it was submitted for publication. A definitive version was subsequently published here: https://doi.org/10.1109/ASPDAC.2018.8297363



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