Flexible Compilation and Refinement of Asynchronous Circuits
2023 28th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)
We present compilation and refinement techniques for translating parallel programs with message passing into asynchronous circuits. Instead of compiling programs directly into circuits using a fixed protocol and circuit family – as is traditionally done – we compile programs into a circuit-neutral model consisting of communication channels with storage, called Links, and storage-free computation modules, called Joints. We refine this model into a gate-level circuit by reducing storage and selecting protocols and circuit families. The final circuits combine 2- and 4-phase protocols and various circuit families. We give two refinement examples. The first refinement safely removes data storage from Links to improve circuit area and power. The second refinement safely splits atomic Joint actions to improve circuit analysis. Both refinements introduce 4-phase protocols for which we give a formal Link-Joint model and circuits in Click, Set-Reset, and GasP. We are implementing this compile then refine approach as a shallow embedding in an open-source design flow.
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Esimai, E., & Roncken, M. (2023). Flexible Compilation and Refinement of Asynchronous Circuits. 2023 28th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). https://doi.org/10.1109/async58294.2023.10239623