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Conference Proceeding

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Reversible logic, Logic synthesis, Logic circuits


A reversible gate maps each output vector into a unique input vector and vice versa. The importance of reversible logic lies in the technological necessity that most "near-future" and all long-term future technologies will have to use reversible gates in order to reduce power. In this paper, a new generalized k*k reversible gate family is proposed. A synthesis method for multi-output (factorized) ESOP using cascades of the new gate family is presented. For utilizing the benefit of product sharing among the ESOPs, two graph-based data structures -connectivity tree and implementation graph are used. Experimental results with some MCNC benchmark functions show that the number of gates in the multioutput ESOP cascades is almost equal to the number of products in the multi-output ESOP. However, this cascaded realization of multi-output ESOP generates a large number of garbage outputs and requires a large number of input constants, which need to be reduced in the future research. This synthesis method is technology-independent and can be used in association with any known or future reversible technology.


Paper originally presented at the 6th International Symposium on Representations and Methodology of Future Computing Technologies (RM'2003), held in Trier, Germany, in March 2003, and subsequently included in its proceedings.

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