TSV- and Delay-Aware 3D-IC Floorplanning

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Analog Integrated Circuits and Signal Processing

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We propose a novel floorplanning algorithm for 3D ICs with through-silicon vias (TSVs) that directly optimizes delay due to wires and TSVs. We include the non-negligible impact of area occupied by TSVs, perform nets-to-TSVs assignment, and use physical dimensions of TSVs and wires for delay calculations. Our floorplanning is based on co-placement of TSV islands with circuit blocks and is performed under fixed-outline constraints. The total delay is a direct optimization goal in the presented delay-aware 3D floorplanning and accounts for the RC delay impact of TSVs on the delay of each individual net during the nets-to-TSVs assignment. Therefore, compared to traditional wirelength-aware floorplanning, which separately minimize wirelength and the number of TSVs, the proposed approach results in more effective delay minimization. Our experimental results show improved solution quality with up to 9 % shorter wirelength and an average 40 % reduction in the number of TSVs as compared to most recent publications. Total delay reduces between 10 and 12 % when the delay, instead of wirelength and the number of TSVs separately, is minimized.



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