Synthesis of Memristive Circuits Based on Stateful IMPLY Gates Using an Evolutionary Algorithm With a Correction Function

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Nanoscale Architectures (NANOARCH), 2016 IEEE/ACM International Symposium on

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Synthesis of stateful memristor-based logic circuits is realized with a multi-stage evolutionary algorithm (IMP_MSEA) which minimizes the total circuit delay. This is done by minimizing the number of pulses to control the circuit. We assume different numbers of working memristors in the circuit and compare the delay results for each. The error of the synthesized circuit is the number of min-terms that differ between the truth table of the function of the resultant circuit and the truth table that specifies this circuit. We formulate a circuit minimization problem in which error should be zero or should be restricted to a small value. The system uses the concept of correction functions when the error is very low and a new round of evolution starts for the correcting function. The logic circuit design includes coding and initialization methods to reduce illegal and redundant solutions of random initial population. Experiments with 2 to 11 input single-output functions demonstrate that the algorithm can deal with various assumed numbers of working memristors and for many benchmark functions it significantly reduces the delay.



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