Utilizing Sneak Paths for Memristor Test Time Improvement
IETE Journal of Research
Memristor technology is becoming an attractive option for memory architectures, in-memory computing, and logic applications due to their non-volatility, high density, and low power operation. However, these memristor-based devices are prone to defects because of the non-deterministic nature of nano-scale fabrication. This research describes a methodology for testing memristor circuits for fault detection and fault diagnosis using a unique property of memristor crossbar circuits – sneak paths. This research focuses on the stuck-at low resistance and stuck-at high resistance faults for our analysis. A 3 × 3 crossbar array was used as an example to demonstrate our fault dictionary-based diagnosis approach with improved test time. Our results show that fault diagnosis can be achieved only in three test vectors for the best case and a worst-case of m + 1 test vectors for an m × n array where m > n.
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Joshi, R., & Acken, J. M. (2021). Utilizing Sneak Paths for Memristor Test Time Improvement. IETE Journal of Research, 1–10. https://doi.org/10.1080/03772063.2021.1883483