Title

Detection Limit for Intermediate Faults in Memristor Circuits

Published In

2021 22nd International Symposium on Quality Electronic Design (ISQED)

Document Type

Citation

Publication Date

4-2021

Abstract

Memristor crossbar structures are widely used in logic, memory, security, and neuromorphic applications. It becomes necessary to test these devices for faults since they are prone to high defect densities. In this paper, we introduce a new terminology “intermediate faults” in memristor circuits. Intermediate faults are faults whose memristor resistance values lie between low resistance state (LRS) and High resistance state (HRS) values. This paper extends the fault detection method for HRS/LRS stuck-at faults to detecting intermediate faults using sneak paths in memristor circuits. We describe the importance of setting the detection limit for testing intermediate faults. Our simulation results present the detection limit value for intermediate resistances using five long and three long sneak paths in a 3x3 crossbar array. Our fault detection scheme can be used for detecting intermediate faults along with stuck-at low resistance and stuck-at high resistance faults.

Rights

© Copyright 2021 IEEE

DOI

10.1109/ISQED51717.2021.9424281

Persistent Identifier

https://archives.pdx.edu/ds/psu/35538

Publisher

IEEE

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