Advisor

Dan Hammerstrom

Date of Award

1-1-2012

Document Type

Thesis

Degree Name

Master of Science (M.S.) in Electrical and Computer Engineering

Department

Electrical and Computer Engineering

Physical Description

1 online resource (xii, 126 pages)

Subjects

Neuromorphics, Inter-chip communication, Address event representation, Integrated circuits -- Very large scale integration -- Design and construction, Cognition -- Computer simulation, Neural networks (Computer science) -- Design and construction

DOI

10.15760/etd.115

Abstract

Continuing advances with VLSI have enabled engineers to build high performance computer systems to solve complex problems. The real-world problems and tasks like pattern recognition, speech recognition, etc. still remain elusive to the most advanced computer systems today. Many advances in the science of computer design and technology are coming together to enable the creation of the next-generation computing machines to solve real-world problems, which the human brain does with ease. One such engineering advance is the field of neuromorphic engineering, which tries to establish closer links to biology and help us investigate the problem of designing better computing machines. A chip built with the principles of neuromorphic engineering is called as neuromorphic chip. Neuromorphic chip aims to solve real-world problems. As the complexity of the problem increases, the computation capability of these chips can become a limitation. In order to improve the performance and accomplish a complex task in the real-world, many such chips need to be integrated into a system. Hence, efficiency of such a system depends on effective inter-chip communication. Here, the work presented aims at building a message-passing network (Digital Fabric) simulator, that integrates many such chips. Each chip represents a binary event-based unit called spiking analog cortical module. The inter-chip communication protocol employed here is called as Address Event Representation. Here, the Digital Fabric is built in three revisions, with different architectures being considered in each revision. The complexity is increased at each iteration stage. The experiments performed in each revision test the performance of such configuration systems and results proves to lay a foundation for further studies. In the future, building a high level simulation model will assist in scaling and evaluating various network topologies.

Persistent Identifier

http://archives.pdx.edu/ds/psu/7964

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