Portland State University. Department of Electrical and Computer Engineering
W. Robert Daasch
Date of Award
Master of Science (M.S.) in Electrical and Computer Engineering
Electrical and Computer Engineering
1 online resource (vii, 67 pages)
Integrated circuits -- Testing, Machine learning, Computer adaptive testing
This thesis reports the performance of a simple classifier as a function of its training data set. The classifier is used to remove analog tests and is named the Test Removal Classifier (TRC).
The thesis proposes seven different training data set designs that vary by the number of wafers in the data set, the source of the wafers and the replacement scheme of the wafers. The training data set size ranges from a single wafer to a maximum of five wafers. Three of the training data sets include wafers from the Lot Under Test (LUT). The training wafers in the data set are either fixed across all lots, partially replaced by wafers from the new LUT or fully replaced by wafers from the new LUT.
The TRC's training is based on rank correlation and selects a subset of tests that may be bypassed. After training, the TRC identifies the dies that bypass the selected tests. The TRC's performance is measured by the reduction in over-testing and the number of test escapes after testing is completed. The comparison of the different training data sets on the TRC's performance is evaluated using production data for a mixed-signal integrated circuit.
The results show that the TRC's performance is controlled by a single parameter- the rank correlation threshold.
Hassan Ranganath, Nagarjun, "Training Set Design for Test Removal Classication in IC Test" (2014). Dissertations and Theses. Paper 2028.