Advisor

Malgorzata E. Chrzanowaska-Jeske

Date of Award

1992

Document Type

Thesis

Degree Name

Master of Science (M.S.) in Electrical Engineering

Department

Electrical Engineering

Physical Description

1 online resource (111 p.)

Subjects

Computer algorithms, Microprocessors -- Design and construction, Computer-aided design, Cypress CY7C361 (Microprocessor)

DOI

10.15760/etd.6102

Abstract

In this thesis, we describe an architecture-driven fitting algorithm for an Application-Specific EPLD, the CY7C361, from Cypress Semiconductor. Traditional placement and routing tools for PLDs perform placement and routing separately. Several placement possibilities are created and the router tries to realize the connections between the physical locations of the cells on the chip. The Cypress CY7C361 has a very unique chip architecture with a highly limited connectivity between the physical cells. Therefore, it is necessary to consider the mutability when the placement of cells is performed. The combination of the two stages is called fitting. The specific architecture-dependent constraints, imposed on the connectivity of the CY7C361 chip were used to develop a hierarchical partitioning structure of the algorithm. This approach limits very effectively the solution space in the early stage of the search for a solution of the fitting problem. The partitioning approach for the fitting algorithm is not limited on the Cypress CY7C361. It can be applied to other architectures with similar connectivity restrictions, too.

Description

If you are the rightful copyright holder of this dissertation or thesis and wish to have it removed from the Open Access Collection, please submit a request to pdxscholar@pdx.edu and include clear identification of the work, preferably with URL

Persistent Identifier

http://archives.pdx.edu/ds/psu/24355

Share

COinS