Advisor

Marek A. Perkowski

Date of Award

6-9-1994

Document Type

Thesis

Degree Name

Master of Science (M.S.) in Electrical and Computer Engineering

Department

Electrical and Computer Engineering

Physical Description

1 online resource (2, viii, 173 p.)

Subjects

Cellular automata, Gate array circuits -- Design and construction, Programmable logic devices -- Design and construction

DOI

10.15760/etd.6587

Abstract

Most existing computers today are built upon a subset of the arithmetic system which is based upon the foundation of set theory. All formal systems can be expressed in terms of arithmetic and logic on current arithmetic computers through an appropriate model, then work with the model using software manipulation. However, severe speed degradation is the price one must pay for using a software-based approach, making several high-level formal systems impractical. To improve the speed at which computers can implement these high-level systems, one must either design special hardware, implementing specific operations much like math and image processing coprocessors, or execute operations upon multiple processors in a parallel fashion. Due to the increase in developing applications for the manipulation of logic functions, an interest in the logic machine has arisen. Many applications such as logic optimization, simulation, pattern recognition and image processing can be better implemented with a logic machine. This thesis proposes the design, hardware realization, and testing of the iterative logic unit (ILU) of the Cube Calculus Machine II (CCM2). The CCM2 is a general purpose computer with an architecture that emphasizes a data path designed to execute operations of cube calculus, a popular algebraic model used in the minimization of Boolean functions. The ILU is an iterative logic array of cells (ITs) using internal distributed control, enabling the execution of basic cube operations, while the Control Unit (CU) handles global signals from the host computer. The ILU of the CCM2 has been realized in hardware using Xilinx Logic Cell Arrays (LCAs). FPGAs offer the logic density and versatility of gate arrays, with the off-the shelf availability and time-to-market advantages of standard user-programmable devices. These devices can be reconfigured, allowing multiple revisions and future design generations to accommodate the same device, thus saving design and production costs, an ideal solution to the resource and financial problems plaguing the University environment.

Description

If you are the rightful copyright holder of this dissertation or thesis and wish to have it removed from the Open Access Collection, please submit a request to pdxscholar@pdx.edu and include clear identification of the work, preferably with URL

Persistent Identifier

https://archives.pdx.edu/ds/psu/27675

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