First Advisor

Malgorzata Chrzanowska-Jeske

Date of Publication

Winter 3-15-2019

Document Type


Degree Name

Doctor of Philosophy (Ph.D.) in Electrical and Computer Engineering


Electrical and Computer Engineering


Carbon nanotubes, Field-effect transistors, Delay faults (Semiconductors), Logic design, Mathematical optimization



Physical Description

1 online resource (xv, 124 pages)


Carbon nanotube field-effect transistors (CNFETs) are considered to be promising candidate beyond the conventional CMOSFET due to their higher current drive capability, ballistic transport, lesser power delay product and higher thermal stability. CNFETs show great potential to build digital systems on advanced technology nodes with big benefits in terms of power, performance and area (PPA). Hence, there is a great need to develop proven models and CAD tools for performance evaluation of CNFET-based circuits. CNFETs specific parameters, such as number of tubes, pitch (spacing between the tubes) and diameter of CNTs determine current driving capability, speed, power consumption and area of circuits and play a significant role in accurate PPA evaluation. Furthermore, count and density variations in carbon nanotubes (CNTs) due to manufacturing limitations, like the presence of metallic tubes in the CNFET channel, pose major obstacles to robust and energy-efficient CNFET digital circuit designs and degrade the anticipated PPA benefits. CNFET-based circuits can suffer from large performance variations and reduction in functional yield due to these variations in CNFETs. Moreover, modeling the CNFET parameters, CNT variations and etching techniques for CNTs create additional complexity during performance optimization. Hence, for realistic optimization of CNFET circuit's performance, it is imperative to incorporate the impact of these parameters and variations.

We present a capacitance-based Logical Effort (LE) framework to investigate design issues of high-speed and low-power circuit designs implemented by considering specific requirements and challenges of the CNFET technology. The LE technique is widely recognized as a pedagogical method to quickly estimate and optimize the propagation delay and transition time in CMOS circuits equivalently without performing transient simulations and detailed delay calculations. In this thesis, we propose novel delay models [Pitch-Aware Logical Effort (PALE) and Position-Aware Pitch Factor (PAPF)] for fast and accurate performance evaluation by including the impact due to CNFET-specific parameters and CNT variations.

1. Ideal case (CNTs variations are not considered):

During our research on CNFET-based circuits, we analyzed the impact of CNFET specific parameters, such as CNTs count, diameter and spacing between tubes, on the performance of CNFET-based circuits. The screening effect is critical to take into account for accurate performance evaluation. Hence, PALE model is developed by extending LE formulation to include influence of CNFET specific parameters.

2. Realistic case (CNTs variations are considered):

We have studied CNFET-based logic gates and circuits in the presence of major CNTs variations using Monte Carlo simulations. The removal of the initially present unwanted metallic tubes, by the known processing techniques, causes non-uniformity of CNT density in the channel. Such variations in the number of CNTs impact circuit performance and functional yield. We develop variation-aware model (PAPF) based on LE technique to include impact of CNTs variations on the delay of large CNFET-based circuits.

Our developed models are correlated with SPICE simulations using different types of gates and circuits with an average error of 3% and 5% for ideal and realistic cases respectively. Our framework is capable of estimating performance more than 100x faster as compared to SPICE simulations methods.

Furthermore, using our models (PALE and PAPF), we present an optimization tool to minimize the area and delay product (ADP) of CNFET circuits. We deploy circuit-level techniques (CLT) prior to the optimizing the tubes (CNTs) in the logic gates to achieve highly optimized solution with global approach. For better optimization of the circuits, the impact of wire parasitic in estimating the delay of the individual gates is included as well. Our optimization tool results in maximum and average delay improvement by 27% and 17% respectively, and 2.5X reduction in area for standard ISCAS and OpenSPARC benchmark circuits. Fast and fairly accurate delay computation in our optimization framework offers great runtime benefits as compared to state-of-the-art SPICE simulation and statistical-based methods.

Finally, we propose more accurate probabilistic model for yield estimation which incorporates the impact of screening effect on the functional yield after the removal of metallic tubes.

Overall, the objective of this thesis is to develop comprehensive LE-based framework and optimization tool and methodology which comprehend CNFET specific parameters for accurate performance evaluation as well as estimation of delay, power, functional yield and ADP optimization in presence of CNTs variations. Our models are easily scalable to future technology nodes.

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