Advisor

Malgorzata Chrzanowska-Jeske

Date of Award

4-24-1996

Document Type

Thesis

Degree Name

Master of Science (M.S.) in Electrical and Computer Engineering

Department

Electrical and Computer Engineering

Physical Description

1 online resource (vii, 67 p.)

Subjects

Integrated circuits -- Design and construction

DOI

10.15760/etd.7113

Abstract

As datapath chips such as microprocessors and digital signal processors become more complex, efficient CAD tools that preserve the regularity of datapath designs and result in small layout area are required. The standard-cell placement techniques ignore the regularity of datapath designs and hence give inefficient layouts. This has necessitated the development of new techniques for datapath module placement. We developed a layout synthesis tool DataPathLAYOUT, for the bit-slice datapath logic designed using standard-cell libraries. We developed fast and area efficient heuristics for placing the cells in a bit-slice such that the regularity of datapath circuits is preserved and the number of channels in which a control signal is routed is minimized. The placement heuristics proposed here are general and also applicable to regular logic like systolic arrays. In addition, we propose a novel window- based heuristic, applicable to datapath and non-datapath circuits, for global routing of multi-terminal nets. We compared the area and run-time efficiency of the DPLAYOUT with an existing standard-cell placement and routing tool. We achieved 98-99% improvement in placement time, 28-33% improvement in area and 8-80% in total time. We conducted some experiments and demonstrated that for standard-cell based datapath designs, bit-slice-based layout generation approach is superior to non-bit-slice-based layout generation approach both in terms of area and run-time. Finally, by providing interface to Verilog hardware description language, we developed a general tool which can be easily integrated with any highlevel synthesis system. This tool is critical in any Datapath Silicon Compiler, to generate mask geometries from the behavioral level input specifications written in a hardware description language.

Description

If you are the rightful copyright holder of this dissertation or thesis and wish to have it removed from the Open Access Collection, please submit a request to pdxscholar@pdx.edu and include clear identification of the work, preferably with URL

Persistent Identifier

https://archives.pdx.edu/ds/psu/30428

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