Advisor

Portland State University. Dept. of Electrical Engineering

Date of Award

3-19-1997

Document Type

Thesis

Degree Name

Master of Science (M.S.) in Electrical and Computer Engineering

Department

Electrical Engineering

Physical Description

1 online resource, (151p.)

Subjects

Application-specific integrated circuits -- Design and construction, Metal oxide semiconductors, Complementary -- Design and construction

DOI

10.15760/etd.7249

Abstract

Consumers demand for products with ever-increasing functionality, performance, and longer battery life is making low power a critical factor in most system designs. Lowerpower designs are less expensive to produce, more reliable, and cost less to operate - factors which create a real competitive advantage. As a result, ASIC designers are demanding better ways to analyze the power of their designs.

In this thesis, an ASIC Power Analysis System (APAS) is developed. APAS is an interactive simulation-based power analysis tool. Using a non-intrusive design technique, APAS can dynamically "snap on" to an existing simulation environment. APAS currently supports three ASIC simulators: QuickSim II, QuickHDL, and Verilog-XL, all with a common library.

Diagnostics is one of the key features in designing APAS. APAS's hierarchical capabilities can be used to find out which blocks in the design are consuming the most power. The designer can then focus on reducing power in these blocks. Analyzing the dynamic behavior of the circuit is also key to power reduction. APAS can dynamically trace the power consumption of any block in the design, giving the user a graphical representation of the periods of high and low activity.

The key to accuracy in APAS is the power models. APAS's power models represent dynamic switching, dynamic short-circuit and static currents. To Achieve optimum accuracy, APAS's models account for input slew, load and internal state. APAS's power models are written in the Power Modeling Format (PMF). PMF's combination of equations and interpolated tables provide the means to capture the most detailed cell characterization data under varying slew, load and state conditions. PMF is designed to support not only gates but also 1/0 cells, RAMs, and higher-level macros.

Description

If you are the rightful copyright holder of this dissertation or thesis and wish to have it removed from the Open Access Collection, please submit a request to pdxscholar@pdx.edu and include clear identification of the work, preferably with URL.

Persistent Identifier

https://archives.pdx.edu/ds/psu/30833

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