First Advisor

Malgorzata Chrzanowska-Jeske

Term of Graduation

Winter 2022

Date of Publication


Document Type


Degree Name

Doctor of Philosophy (Ph.D.) in Electrical and Computer Engineering


Electrical and Computer Engineering





Physical Description

1 online resource (xix, 231 pages)


Various emerging technologies have shown great potential of supplementing silicon transistors as Moore's law slows down. One such disruptive technology, Carbon Nanotube Field Effect Transistors (CNFET), among others, promises increased speed and integration with reduced power consumption. However, due to a limited controllability over the Carbon Nano-tube(CNT) growth process, CNFETs show large variations in their performance and behavior. It is therefore difficult to predict and model their behavior while design suggestions are also challenging. CNT variations are important for a realistic delay modelling. Due to the presence of CNT-specific variations, conventional CMOS evaluation techniques cannot be used for CNFETs.

This work focuses on predicting delay, power and functional yield of CNFET-based circuits under CNT variations, as accurately as possible using a statistical approach. Along with extensively studied CNT variations, we model CNT length variation for the first-time. Tube length variation is especially important if the same tube is used in a number of aligned transistors -- called tube correlation. One of the well-known approaches to deal with variations is redundancy.

Redundancy, however, comes at the cost of increased power and area. To limit redundancy, we propose adding redundant tubes only to transistors on critical paths. The challenge with this approach is that with variations, critical paths may vary under CNT variations. Therefore, to consider all potential critical paths under assumed variations and add redundancy to all of them, we developed an efficient algorithm for fast identification of all paths that can become critical in the presence of variations.

This algorithm adds an optimized number of redundant tubes to critical-paths transistors only to minimize power increase at no additional area overhead and is much faster than time intensive Monte Carlo simulations. Our results on a set of ISCAS 85 benchmarks, show that, with our approach, we can achieve delay almost identical with delay without tube variations, >99.99% functional yield and less than 2% increase in circuit power.

Even with improved next-generation logic devices like CNFETs, system level performance will remain severely constrained by the growing interconnect performance bottleneck. To overcome this bottleneck, revolutionary digital system architectures with highly fine-grained integration of disparate technologies is required. Three dimensional (3D) integrated circuits (IC) are proposed as one way to address this problem among many other advancements in wafer level packaging techniques. While 3DIC technology has a lot to offer, lack of effective heat removal techniques continue to be a critical challenge for 3D IC circuit design. This is because up to millions of components produce a great quantity of heat in such a compact space of an integrated circuit, the temperature may sharply increase to significantly deteriorate the performance. In addition, early physical design stages like floor planning, being probabilistic, need thousands of runs to reach a desired stage of optimization. Including thermal analysis in the third dimension only further prolongs the solution evaluation in early design. We thus focus on developing fast methods for thermal goodness evaluation of 3DICs in early stages of physical design.

We propose a power based metric to quickly evaluate the relative thermal goodness of two given floorplans. The proposed algorithm is 29X faster on a grid size of 64x64x4 for GSRC benchmarks compared to a more accurate simulation based tool like Hotspot [1].

Moreover, each device layer in the 3D IC is at a different temperature and varying wire distribution. Ignoring the impact of temperature and interconnect density on 3D interconnect performance may lead to generating severely sub-optimal solution selection.

Experimental results on GSRC benchmarks show 40% underestimation in interconnect delay on average and 3.6X-4.5X variation in buffer count using room temperature parameters. An average difference of 19% in total delay in GSRC benchmarks using the proposed true thermal-aware and wire-density-aware interconnect performance evaluation when compared to only thermal-aware delay, emphasizes the need for a more realistic evaluation the 3D interconnect performance to avoid sub-optimal solution generation. Therefore, we incorporate thermal-delay aware floorplanning while also considering the effective wire density distribution to enable a more realistic evaluation of the interconnect performance to appropriately guide the 3D floorplan optimization.

This work is thus a step towards generating both thermally optimal 3D solutions and variation-tolerant reliable CNFET circuits.


©2022 Satya Keerthi Vendra

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