Advisor

W. Robert Daasch

Date of Award

1-1-2012

Document Type

Thesis

Degree Name

Master of Science (M.S.) in Electrical and Computer Engineering

Department

Electrical and Computer Engineering

Physical Description

1 online resource (vi, 52 pages)

Subjects

Fault aliasing, Fault cones, Triple modular redundancy, Digital integrated circuits -- Testing, Integrated circuits -- Fault tolerance, Redundancy (Engineering)

DOI

10.15760/etd.64

Abstract

The test of digital integrated circuits compares the test pattern results for the device under test (DUT) to the expected test pattern results of a standard reference. The standard response is typically obtained from simulations. The test pattern and response are created and evaluated assuming ideal test conditions. The standard response is normally stored within automated test equipment (ATE). However the use of ATE is the major contributor to the test cost. This thesis explores an alternative strategy to the standard response. As an alternative to the stored standard response, the response is estimated by fault tolerant technique. The purpose of the fault tolerant technique is to eliminate the need of standard response and enable online/real-time testing. Fault tolerant techniques use redundancy and majority voting to estimate the standard response. Redundancy in the circuit leads to fault aliasing. Fault aliasing misleads the majority voter in estimating the standard response. The statistics and phenomenon of aliasing are analyzed for benchmark circuits. The impact of fault aliasing on test with respect to coverage, test escape and over-kill is analyzed. The results show that aliasing can be detected with additional test vectors and get 100% fault coverage.

Persistent Identifier

http://archives.pdx.edu/ds/psu/8121

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