Sponsor
This research is partially supported by Semiconductor Research Corporation Contract: 2932.001 and a gift from Intel Corporation.
Published In
ASPDAC '23
Document Type
Conference Proceeding
Publication Date
2023
Subjects
Compilers (Computer programs), Computer software -- Verification
Abstract
Agile hardware design enables designers to produce new design iterations efficiently. Equivalence checking is critical in ensuring that a new design iteration conforms to its specification. In this paper, we introduce an equivalence checking framework for hardware designs represented in HalideIR. HalideIR is a popular intermediate representation in software domains such as deep learning and image processing, and it is increasingly utilized in agile hardware design.We have developed a fully automatic equivalence checking workflow seamlessly integrated with HalideIR and several optimizations that leverage the incremental nature of agile hardware design to scale equivalence checking. Evaluations of two deep learning accelerator designs show our automatic equivalence checking framework scales to hardware designs of practical sizes and detects inconsistencies that manually crafted tests have missed.
Rights
© 2023 Copyright held by the owner/author(s).
This work is licensed under a Creative Commons Attribution 4.0 International License.
Locate the Document
DOI
10.1145/3566097.3567843
Persistent Identifier
https://archives.pdx.edu/ds/psu/39631
Citation Details
Wang, Y., Xie, F., Yang, Z., Cocchini, P., & Yang, J. (2023, January). An Equivalence Checking Framework for Agile Hardware Design. In Proceedings of the 28th Asia and South Pacific Design Automation Conference (pp. 26-32).