Document Type
Conference Proceeding
Publication Date
5-2004
Subjects
Reversible computing, Quantum computers, Logic circuits -- Design and construction
Abstract
It is believed that quantum computing will begin to have an impact around year 2010. Much work is done on physical realization and synthesis of quantum circuits, but nothing so far on the problem of generating tests and localization of faults for such circuits. Even fault models for quantum circuits have been not formulated yet. We propose an approach to test generation for a wide category of fault models of single and multiple faults. It uses deterministic and probabilistic tests to detect faults. A Fault Table is created that includes probabilistic information. If possible, deterministic tests are first selected, while covering faults with tests, in order to shorten the total length of the test sequence. The method is applicable to both binary and ternary quantum circuits. The system generates test sequences and adaptive trees for fault localization for small binary and ternary quantum circuits.
Persistent Identifier
http://archives.pdx.edu/ds/psu/12829
Citation Details
Aligala, Sowmya, Sreecharani Ratakonda, Kiran Narayan, Kanagalakshmi Nagarajan, Martin Lukac, Jacob Biamonte, and Marek Perkowski. "Deterministic and Probabilistic Test Generation for Binary and Ternary Quantum Circuits." Proceedings ULSI (2004)
Description
Originally presented at the 13th International Workshop on Post-Binary ULSI Systems, May 19, 2004, University of Toronto, Toronto, Canada, and subsequently included in its proceedings.