Published In
Multiple-Valued Logic (ISMVL), 2011 41st IEEE International Symposium on
Document Type
Conference Proceeding
Publication Date
5-2011
Subjects
Logic synthesis, Logic circuits -- Design and construction
Abstract
In this paper, we concentrate on design of synchronous counters directly from reversible gates.
DOI
10.1109/ISMVL.2011.25
Persistent Identifier
http://archives.pdx.edu/ds/psu/12896
Citation Details
Perkowski, Marek and Khan, Mozammel H.A., "Synthesis of Reversible Synchronous Counters" (2011). Electrical and Computer Engineering Faculty Publications and Presentations. 203.
http://archives.pdx.edu/ds/psu/12896
Description
This is the author's version of a paper which was subsequently published as "Synthesis of Reversible Synchronous Counters." Multiple-Valued Logic (ISMVL), 2011 41st IEEE International Symposium on. IEEE, 2011. Version of record may be found at http://ieeexplore.ieee.org/xpls/abs_all.jsp arnumber=5954240 Copyright (2011) IEEE . Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.