Logical Effort Model for CNFET Circuits with CNTs Variations

Published In

Proceedings of the 15th IEEE International Conference on Nanotechnology

Document Type

Citation

Publication Date

7-2015

Subjects

Carbon nanotubes, Nanostructured materials, Logic design, Delay faults (Semiconductors)

Abstract

Carbon Nano-Tube Field Effect Transistors (CNFETs) offer promising solutions beyond conventional CMOS FETs. CNFETs have higher current drive capability, ballistic transport, lesser power delay product and higher thermal stability. The delay evaluation in CNFETs may not be trivial due to additional CNFET specific parameters, such as number of tubes, pitch (spacing between the tubes) and the diameter of CNTs that determines current driving capability. Moreover, the initial presence of metallic tubes and their desired removal may result in non-uniform pitch distribution. This random pitch behavior depends on the percentage of metallic tubes and the removal technique deployed. The necessary removal of the metallic tube may have significant impact on the performance of the circuit. In this paper, we propose a closed-form model to capture the impact of metallic tubes and the removal techniques on the gate and circuit delay. The influence of CNT position in the tube array of the gate on the gate-delay is captured in Logical Effort (LE) model. Our model results in fairly accurate delay estimation with an average error 2% - 5% for set of tested CNFET circuits.

Description

Published in Proceedings of the 15th IEEE International Conference on Nanotechnology, held July 2015, Rome, Italy. © Copyright 2016 IEEE - All rights reserved.

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Unaffiliated researchers can access the work here: http://dx.doi.org/10.1109/NANO.2015.7388848

DOI

10.1109/NANO.2015.7388848

Persistent Identifier

http://archives.pdx.edu/ds/psu/16642

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