Document Type
Pre-Print
Publication Date
2015
Subjects
Digital integrated circuits -- Design and construction, Asynchronous circuits, Logic design. Discrete-time systems
Abstract
This paper introduces ARCtimer, a framework for modeling, generating, verifying, and enforcing timing constraints for individual self-timed handshake components. The constraints guarantee that the component’s gate-level circuit implementation obeys the component’s handshake protocol specification. Because the handshake protocols are delayinsensitive, self-timed systems built using ARCtimer-verified components are also delay-insensitive. By carefully considering time locally, we can ignore time globally. ARCtimer comes early in the design process as part of building a library of verified components for later system use. The library also stores static timing analysis (STA) code to validate and enforce the component’s constraints in any self-timed system built using the library. The library descriptions of a handshake component’s circuit, protocol, timing constraints, and STA code are robust to circuit modifications applied later in the design process by technology mapping or layout tools. In addition to presenting new work and discussing related work, this paper identifies critical choices and explains what modular timing verification entails and how it works.
DOI
10.1007/s11390-016-1613-y
Persistent Identifier
http://archives.pdx.edu/ds/psu/16858
Citation Details
Park, Hoon; He, Anping; Roncken, Marly; Song, Xiaoyu; and Sutherland, Ivan, "Modular Timing Constraints for Delay-Insensitive Systems" (2015). Electrical and Computer Engineering Faculty Publications and Presentations. 306.
http://archives.pdx.edu/ds/psu/16858
Description
Authors' version of an article that was subsequently published in Journal of Computer Science and Technology, January 2016, Volume 31, Issue 1, pages 77-106.
Version of record may be found at http://link.springer.com/article/10.1007%2Fs11390-016-1613-y