Through Silicon Via-Aware Layout Design and Power Estimation in Sub-45 Nanometer 3D CMOS IC Technologies

Authors

S. Mohapatra, Portland State UniversityFollow
Satya K. Vendra, Portland State University
Malgorzata Chrzanowska-Jeske, Portland State UniversityFollow

Published In

2018 IEEE 13th Nanotechnology Materials and Devices Conference (NMDC)

Document Type

Citation

Publication Date

1-10-2019

Abstract

We analyze the impact of through-silicon vias (TSVs) downsizing and future CMOS nanotechnology scaling on interconnect delay and power in 3-dimensional integrated circuits (3DICs). We study three different TSV sizes of 3μ, 1.5μ and 0.5μ at three diverse technology nodes of 45nm, 32nm and 22nm. These technology variations are considered to investigate the impact on interconnect performance and power in 3D ICs. Our discussion also includes the impact of TSV cluster size variation on TSV capacitance which is important for early performance optimization in any given technology. A delay-aware 3D floorplanning tool with dynamic TSV clustering is used to simultaneously optimize TSV footprint and TSV cluster distribution. Our results show with scaling from 45nm to 22nm., delay, for all TSV sizes increases by ~41 %, while power reduces by ~46%.

Description

© Copyright 2019 IEEE - All rights reserved.

Locate the Document

https://doi.org/10.1109/NMDC.2018.8605914

DOI

10.1109/NMDC.2018.8605914

Persistent Identifier

https://archives.pdx.edu/ds/psu/29051

Citation Details

S. Mohapatra, S. K. Vendra and M. Chrzanowska-Jeske, "Through Silicon Via-Aware Layout Design and Power Estimation in Sub-45 Nanometer 3D CMOS IC Technologies," 2018 IEEE 13th Nanotechnology Materials and Devices Conference (NMDC), Portland, OR, 2018, pp. 1-4.