Memristor Based 8-Bit Iterative Full Adder with Space-Time Notation and Sneak-Path Protection

Authors

Kamela Choudhury Rahman, Portland State UniversityFollow
Masoodur Rahman Khan, Ahsanullah University of Science and Technology
Marek A. Perkowski, Portland State UniversityFollow

Published In

2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)

Document Type

Citation

Publication Date

10-2017

Abstract

Memristor technology is receiving an increased attention as a potential solution to meet the scaling demands in integrated circuit design. Memristor provides advantages like high-density, low-power, non-volatility and good scalability. In this paper, an 8-bit iterative full adder design is proposed that uses space-time based circuit notation. It uses stateful logic with memristive nanowire crossbar. The proposed design provides good protection against sneak-path current. The 8-bit full adder requires only 165 micro pulses to perform its operation with greatly reduced sneak-path.

Description

©2017 IEEE

Locate the Document

https://doi.org/10.1109/MWSCAS.2017.8053018

DOI

10.1109/MWSCAS.2017.8053018

Persistent Identifier

https://archives.pdx.edu/ds/psu/30663

Citation Details

Rahman, K. C., Khan, M. R., & Perkowski, M. A. (2017, August). Memristor based 8-bit iterative full adder with space-time notation and sneak-path protection. In 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS) (pp. 695-698). IEEE.