Fault Coverage Analysis Using Sneak Path Based Testing in Memristor Circuits

Authors

Rasika Joshi, Intel CorporationFollow
John M. Acken, Portland State UniversityFollow

Published In

2022 IEEE 31st Microelectronics Design & Test Symposium (MDTS)

Document Type

Citation

Publication Date

2022

Abstract

Testing memristor crossbar arrays is required to ensure high quality. However, inefficient testing can be prohibitively expensive. To evaluate the quality and efficiency of a test requires identifying the underlying relationship between fault coverage and test time as measured by faults detected per added test vector. This work describes a test methodology that utilizes sneak paths for efficient test generation. This work further describes the relationship between added test vectors and improved fault coverage for the efficient test generation methodology.

Rights

Copyright 2022 IEEE

Locate the Document

https://doi.org/10.1109/MDTS54894.2022.9826959

DOI

10.1109/MDTS54894.2022.9826959

Persistent Identifier

https://archives.pdx.edu/ds/psu/38131

Publisher

IEEE

Citation Details

Joshi, R., & Acken, J. M. (2022, May). Fault Coverage Analysis using Sneak Path based Testing in Memristor Circuits. In 2022 IEEE 31st Microelectronics Design & Test Symposium (MDTS) (pp. 1-6). IEEE.