Published In
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1–1.
Document Type
Post-Print
Publication Date
8-2022
Subjects
Dynamic frequency regulation, Energy consumption, GPU, Graphics processing units, Instruction sets, Multi-layer energy optimisation, Optimization, Parallel processing, Power demand, Task analysis, Warps and tasks parallelisms
Abstract
Massive GPU acceleration processors have been used in high-performance computing systems. The Dennard-scaling has led to power and thermal constraints limiting the performance of such systems. The demand for both increased performance and energy-efficiency is highly desired. This paper presents a multi-layer low-power optimisation method for warps and tasks parallelisms. We present a dynamic frequency regulation scheme for performance parameters in terms of load balance and load imbalance. The method monitors the energy parameters in runtime and adjusts adaptively the voltage level to ensure the performance efficiency with energy reduction. The experimental results show that the multi-layer low-power optimisation with dynamic frequency regulation can achieve 40% energy consumption reduction with only 1.6% performance degradation, thus reducing 59% maximum energy consumption. It can further save about 30% energy consumption in comparison with the single-layer energy optimisation.
Rights
© Copyright 2022 IEEE - All rights reserved.
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DOI
10.1109/TCAD.2022.3200528
Persistent Identifier
https://archives.pdx.edu/ds/psu/38427
Citation Details
Published as: Wang, Z., Song, X., Cheng, L., Wan, H., Zhao, W., & Wang, T. (2022). Warp-Aware Adaptive Energy Efficiency Calibration for Multi-GPU Systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1–1. https://doi.org/10.1109/TCAD.2022.3200528
Description
This is the author’s version of a work that was accepted for publication in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1–1. Changes resulting from the publishing process, such as peer review, editing, corrections, structural formatting, and other quality control mechanisms may not be reflected in this document. Changes may have been made to this work since it was submitted for publication. A definitive version was subsequently published in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1–1.