Published In

International Journal of Unconventional Computing

Document Type

Pre-Print

Publication Date

11-3-2024

Subjects

In-Memory Computing

Abstract

Security is a growing problem that needs hardware support. Memristors provide an alternative technology for hardware-supported security implementation. This paper presents a specific technique that utilizes the benefits of hybrid CMOS-memristors technology demonstrated with SHA3 over implementations that use only memristor technology. In the proposed technique, SHA3 is implemented in a set of perpendicular crossbar arrays structured to facilitate logic implementation and circular bit rotation (Rho operation), which is perhaps the most complex operation in SHA3 when carried out in memristor arrays. The Rho operation itself is implemented with CMOS multiplexers (MUXs). The proposed accelerator is standby power-free and circumvents the memory access bottleneck in conventional computers. In addition, our design obscures the intermediate values from the I/O interface and outperforms the state-of-the-art memristor-based designs in terms of size and energy. Demonstrating the memristor implementation of SHA3 provides an impetus for utilizing memristors in information security applications.

Rights

© Copyright the author(s) 2024

Description

This is the author’s version of a work that was accepted for publication. Changes resulting from the publishing process, such as peer review, editing, corrections, structural formatting, and other quality control mechanisms may not be reflected in this document. Changes may have been made to this work since it was submitted for publication. A definitive version was subsequently published as: Aljafar, M. J., Joshi, R., & Acken, J. M. (2024). A 3D Memristor Architecture for In-Memory Computing Demonstrated with SHA3. arXiv preprint arXiv:2402.09545.

DOI

10.32908/ijuc.v19.021123

Persistent Identifier

https://archives.pdx.edu/ds/psu/42696

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