Published In
IEEE Access
Document Type
Post-Print
Publication Date
1-29-2026
Subjects
Computer Architecture, Computer science education, Education courses, Microarchitecture
Abstract
RISC-V is a free and open-standard ISA based on RISC principles, allowing anyone to design, manufacture, and sell RISC-V chips and software. Its flexibility and growing ecosystem have made it popular in research, education, and industry, increasing the need for educational materials. This paper provides an in-depth description of the RVfpga course, which offers a solid introduction to computer architecture using the RISC-V instruction set and FPGA technology. It focuses on providing hands-on experience with real-world RISC-V cores, the VeeR EH1 and EL2 cores, developed by Western Digital and hosted by ChipsAlliance. The course targets students and educators in computing-related fields, enabling them to integrate practical RISC-V knowledge into their curricula. The course materials, which include detailed labs, setup guides, and the full SoC source code in System Verilog, are available for free. Students learn to compile, debug, and run C and assembly programs, to interact with built-in peripherals, to extend the SoC, and to explore microarchitectural features.
Rights
Copyright (c) 2025 The Authors
This work is licensed under a Creative Commons Attribution 4.0 International License.
DOI
10.1109/ACCESS.2026.3658743
Persistent Identifier
https://archives.pdx.edu/ds/psu/44455
Publisher
IEEE
Citation Details
Chaver, D., Harris, S., Pinuel, L., Kindgren, O., Kakakhel, Z., Owen, C., Kravitz, R., Gomez-Perez, J. I., Castro, F., Olcoz, K., Villalba-Moreno, J., Grinshpun, A., Gabbay, F., Seed, L., Duarte, R., López, M., Alonso, Ó., & Owen, R. (2026). The RISC-V FPGA (RVfpga) Teaching Package. IEEE Access, 1–1. https://doi.org/10.1109/access.2026.3658743
Description
This article has been accepted for publication in IEEE Access. This is the author's version which has not been fully edited and content may change prior to final publication.